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g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 1 - features : description : * 4,194,304 words by 4 bits organization. * fast access time and cycle time * low power dissipation. * read-modify-write, ras -only refresh, cas -before- ras refresh, hidden refresh. * 2,048 refresh cycles per 32ms. * available in 300 mil 26(24) soj and tsopii. * 2.5v 0.2v vcc power supply voltage . * all inputs and outputs are lvttl compatible. * extended data-out (edo) page access cycle. * self-refresh capability . (s-version). the glt4160m04 is a high- performance cmos dynamic random access memory containing 16,777,216 bits organized in a x4 configuration. the glt4160m04 offers page cycle access with extended data output. the glt4160m04 has 11 row- and 11 column-addresses, and accepts 2048-cycle refresh in 32 ms. the glt4160m04 provides edo page mode operation which allows for fast data access within a row-address defined boundary, up to 2048 x 4 bits with cycle times as short as 25ns. high performance 60 70 max. ras access time, (t rac ) 60 ns 70 ns max. column address access time, (t aa ) 30 ns 35 ns min. extended data out page mode cycle time, (t pc ) 25 ns 30 ns min. read/write cycle time, (t rc ) 104 ns 124 ns max. cas access time (t cac ) 15 ns 20 ns
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 2 - pin configuration : v cc dq 0 a 0 a 1 a 2 a 3 1 2 3 4 5 6 8 9 10 11 12 13 22 21 19 18 17 16 15 14 26 25 24 23 a 9 a 8 a 7 a 6 oe cas v ss dq 3 dq 1 we ras nc v cc dq 2 a 5 a 4 v ss a 10 v cc dq 0 a 10 a 0 a 1 a 2 a 3 1 2 3 4 5 6 8 9 10 11 12 13 22 21 19 18 17 16 15 14 26 25 24 23 a 9 a 8 a 7 a 6 oe cas v ss dq 3 dq 1 we ras nc v cc dq 2 a 5 a 4 v ss pin descriptions: name function a 0 - a 10 address inputs ras row address strobe cas column address strobe we write enable oe output enable dq 0 - dq 3 data inputs / outputs v cc +2.5v power supply v ss ground nc no connection glt4160m04 300mil 26(24) tsopii glt4160m04 300mil 26(24) soj
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 3 - absolute maximum ratings* capacitance* t a =25 c, v cc =2.5v 0.2v, v ss =0v operating temperature, t a (ambient) .............................................?.0 c to +70 c for extended temperature ?????..-20 c to 85 c storage temperature(plastic)............-55 c to +150 c voltage relative to v ss . .......................-0.5v to + 4.6v short circuit output current...............................20ma power dissipation ...............................................1.0w symbol c in1 c in2 c out para meter address input ras, cas, we, oe data input/output max. 5 7 7 unit pf pf pf *note: operation above absolute maximum ratings can aversely affect device reliability. *note: capacitance is sampled and not 100% tested electrical specifications l all voltages are referenced to gnd. l after power up, wait more than 200 m s and then, execute eight cas -before- ras or ras -only refresh cycles as dummy cycles to initialize internal circuit. block diagram : no.2 clock generator column- address buffer(11) refresh controller refresh counter row address buffers(11) no.1 clock generator 11 11 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 ras 11 11 column decoder data-out buffer data-in buffer sense amplifiers i/o gating 2048 x 1024 x 4 memory array 2048 2048 4 4 4 4 we cas dq 0 dq 1 dq 2 dq 3 oe v dd v ss row decoder 2048 a 0
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 4 - truth table: function ras cas we oe address data-in/out t r t c dq1-dq4 standby h h ? x x x x x high-z read l l h l row col data-out early write l l l x row col data-in read write l l h ? l l ? h row col data- out,data-in edo-page-mode 1st cycle l h ? l h l row col data-out read 2nd cycle l h ? l h l n/a col data-out edo-page-mode 1st cycle l h ? l l x row col data-in early-write 2nd cycle l h ? l l x n/a col data-in edo-page-mode 1st cycle l h ? l h ? l l ? h row col data- out,data-in read-write 2nd cycle l h ? l h ? l l ? h n/a col data- out,data-in ras -only refresh l h x x row n/a high-z hidden refresh read l ? h ? l l h l row col data-out write l ? h ? l l l x row col data-in cbr refresh h ? l l h x x x high-z self refresh h ? l l h x x x high-z
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 5 - dc and operating characteristics (1-2) t a = 0 c to 70 c, -20 c to 85 c v cc =2.5v 0.2v, v ss =0v, unless otherwise specified. sym. parameter test conditions access time min. typ max. unit notes i li input leakage current (any input pin) 0v v in v cc +0.3v (all other pins not under test=0v) -5 +5 m a i lo output leakage current (for high-z state) 0v v out v cc output is disabled (hiz) -5 +5 m a i cc1 operating current, random read/write t rc = t rc (min.) t rac = 60ns t rac = 70ns 80 70 ma 1,2 i cc2 standby current, (ttl) ras , cas at v ih other inputs 3 v ss 1 ma i cc3 refresh current, ras -only ras cycling, cas at v ih t r c = t rc (min.) t rac = 60ns t rac = 70ns 80 70 ma 2 i cc4 operating current, edo page mode ras at v il , cas address cycling:t pc =t pc (min.) t rac = 60ns t rac = 70ns 80 70 ma 1,2 i cc5 refresh current, cas before ras ras , cas address cycling: t rc =t rc (min.) t rac = 60ns t rac = 70ns 80 70 ma 1 i cc6 standby current, (cmos) ras 3 v cc -0.2v, cas 3 v cc -0.2v, all other inputs v ss 200 m a 1 i cc7 self refresh current ras = cas =0.2v, we = oe = a 0 ~a 10 =v cc - 0.2v or 0.2v dq 0 ~dq 3 =v cc -0.2v,0.2v or open 200 m a v il input low voltage -0.3 +0.8 v 3 v ih input high voltage 2.0 v cc +0.3 v 4 v ol output low voltage i ol = 2ma 0.4 v v oh output high voltage i oh = -2ma 1.8 v notes: 1. i cc is dependent on output loading when the device output is selected. specified i cc (max.) is measured with the output open. 2. i cc is dependent upon the number of address transitions specified icc(max.) is measured with a maximum of one transition per address cycle in random read/write and edo fast page mode. 3. specified v il (min.) is steady state operation. during transitions v il (min.) may undershoot to ?0.9v for a period not to exceed 10ns. all ac parameters are measured with v il (min.) 3 v ss and v ih (max.) v cc . 4. specified v ih (max.) is steady state operation . during transitions v ih (max.) may overshoot to v cc +0.9v for a period not to exceed 10ns. all ac parameters are measured with v il (min.) 3 v ss and vih(max.) v cc .
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 6 - ac characteristics t a = 0 c to 70 c , -20 c to 85 c v cc = 2.5 v 0.2v, vih/vil = 2.0/0.8 v, v oh /v ol = 1.6/0.6v an initial pause of 200 m s and 8 cas -before- ras or ras -only refresh cycles are required after power-up. 60 70 parameter symbol min. max. min. max. unit notes read or write cycle time t rc 104 124 ns read modify write cycle time t rwc 140 170 ns ras precharge time t rp 40 50 ns ras pulse width t ras 60 10k 70 10k ns access time from ras t rac 60 70 ns 1, 2, 3 access time from cas t cac 15 20 ns 1, 5, 10 access time from column address t aa 30 35 ns 1, 5, 6 cas to output low-z t clz 3 3 ns cas to output high-z t cez 3 15 3 20 ns ras hold time t rsh 15 20 ns cas hold time t csh 45 50 ns cas pulse width t cas 10 10k 15 10k ns ras to cas delay time t rcd 20 45 20 50 ns ras to column address delay time t rad 15 30 15 35 ns 7 cas to ras precharge time t crp 5 5 ns row address set-up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set-up time t asc 0 0 ns column address hold time t cah 10 15 ns column address to ras lead time t ral 30 35 ns column address hold time referenced to ras t ar 45 50 ns read command set-up time t rcs 0 0 ns read command hold time referenced to cas t rch 0 0 ns 4 read command hold time referenced to ras t rrh 0 0 ns 4 write command set-up time t wcs 0 0 ns 8, 9 write command hold time t wch 10 15 ns write command pulse width t wp 10 15 ns write command to ras lead time t rwl 15 30 ns write command to cas lead time t cwl 10 15 ns
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 7 - ac characteristics 60 70 parameter symbol min. max. min. max. unit notes data set-up time t ds 0 0 ns data hold time t dh 10 15 ns data hold time referenced to ras t dhr 45 50 ns ras to we delay time t rwd 79 94 ns cas to we delay time t cwd 34 44 ns column address to we delay time t awd 49 59 ns cas precharge to we delay t cpwd 54 64 ns ras to cas precharge time t rpc 5 5 ns cas precharge time ( cas before ras counter test cycle) t cpt 20 25 ns access time from cas precharge t cpa 35 40 ns edo page mode cycle time t pc 25 30 ns edo page mode read-modify-write cycle time t prwc 56 71 ns cas precharge time (edo page mode) t cp 10 10 ns ras pulse width (edo page mode only) t rasp 60 100k 70 100k ns ras hold time from cas precharge t rhcp 35 40 ns access time from oe t oea 15 0 20 ns 8 oe to data delay time t oed 15 20 ns oe to output low-z t olz 0 0 ns oe to output high-z t oez 3 15 3 20 ns we to data delay t wed 15 20 ns oe command hold time t oeh 15 20 ns data output hold after cas low t doh 5 5 ns ras to output high-z t rez 3 15 3 20 ns we to output high-z t wez 3 15 3 20 ns oe to cas hold time t och 5 5 ns cas hold time to oe t cho 5 5 ns oe precharge time t oep 5 5 ns we puts width (edo mixed read write cycle) t wpe 5 5 ns cas set-up time for cas -before- ras cycle t csr 5 5 ns
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 8 - 60 70 parameter symbol min. max. min. max. unit notes cas hold time for cas -before- ras cycle t chr 10 15 ns we to ras precharge time ( cas before ras refresh ) t wr p 10 10 ns we to ras hold time ( cas before ras refresh ) t wrh 10 10 ns transition time t t 2 50 2 50 ns refresh period (2,048 cycles) t ref 32 32 ms refresh period (s-version) t refs 128 128 ms ras pulse width ( cas before ras self refresh ) t rass 100 100 m s ras precharge time ( cas before ras self refresh ) t rps 110 130 ns cas hold time ( cas before ras self refresh ) t chs -50 -50 ns
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 9 - test mode cycle 60 70 parameter symbol min. max. min. max. unit notes random read or write cycle time t rc 109 129 ns read-modify-write cycle time t rwc 145 175 ns access time from ras t rac 65 75 ns 1,2,3,7 access time from cas t cac 20 25 ns 1,3,7 access time from column address t aa 35 40 ns 1,2,7 ras pulse width t ras 65 10k 75 10k ns cas pulse width t cas 15 10k 20 10k ns ras hold time t rsh 20 25 ns cas hold time t csh 50 55 ns column address to ras lead time t ral 35 40 ns cas to we delay time t cwd 39 49 ns 8 ras to we delay time t rwd 84 99 ns 8 column address to we delay time t awd 54 64 ns 8 cas precharge to we delay time t cpwd 59 69 ns 8 edo page mode cycle time t pc 30 35 ns edo page mode read-modify-write cycle time t prwc 61 76 ns ras pulse width (edo page cycle) t rasp 65 100k 75 100k ns access time form cas precharge t cpa 40 45 ns 1 oe access time t oea 20 25 ns oe to data delay t oed 20 25 ns oe command hold time t oeh 20 25 ns write command set-up time (test mode in) t wts 10 10 ns write command hold time (test mode in) t wth 10 10 ns
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 10 - notes: 1. measure with a load equivalent to one ttl input and 100 pf. 2. assumes that t rcd t rcd (max.). if t rcd is greater than t rcd (max.), access time will be t aa dominant. 3. assumes that t rad t rad (max.). if t rad is greater than t rcd (max.), access time will be controlled by t cac . 4. either t rrh or t rch must be satisfied for a read cycle. 5. access time is determined by the longest of t aa , t cac and t cpa . 6. assumes that t rad 3 t rad (max.). 7. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, the access time is controlled by t caa and t cac . 8. t wcs , t rwd , t aw d and t cwd are not restrictive operating parameters. 9. t wcs (min.) must be satisfied in an early write cycle. 10. t ds and t dh are referenced to the latter occurrence of cas or we . 11. t t is measured between v ih (min.) and v il (max.). ac-measurements assume t t = 2 ns.
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 11 - read cycle row address column address data-out t rc t ras t rp t crp t csh t rcd t rsh t cas t crp t asr t rah t rad t asc t cah t ral t rch t rrh t ar t rcs t aa t oea t cez t oez t cac t clz t rac don't care v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe v oh- v ol- dq early write cycle note : d out = open t rp t rc t crp t csh t crp t rcd t rsh t cas t asr t rah t rad t asc t cah t ral t cwl t rwl t wcr t wch t wp t wcs t ar t ds t dh t dhr data - in column address row address v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe v ih- v il- dq don't care t ras
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 12 - oe controlled write cycle note : d out = open t rp t rc t crp t csh t crp t rcd t rsh t cas t asr t rah t rad t asc t cah t ral data - in column address row address v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe v ih- v il- dq don't care t ras t rcs t cwl t rwl t wp t ds t oed t oeh t dh read - modify - write cycle t rp t rc t crp t crp t rcd t rsh valid data-out column address row addr. v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe v i/oh- v i/ol- dq don't care t ras valid data-in t cas t asr t rah t rad t asc t cah t csh t awd t cwd t rwl t cwl t wp t oea t clz t cac t aa t rac t dh t ds t oed t oez
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 13 - edo page mode read cycle note : d out = open t rasp t rp t crp t rcd t cas t csh t cp t cas t cas t cas t cp t cp t pc t pc t pc t csr t rah t rad t asc t asc t asc t asc t cah t cah t cah t cah t rcs t rch t rrh t oea t oea t cac t cpa t aa t och t cpa t aa t cac t oep t cho t aa t cac t cpa t clz t olz t rac t cac t doh t oez t oep t oez t oez valid data-out valid data-out valid data-out valid data-out valid data-out v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe dq v oh- v ol- row addr. column address column address col. addr. col. addr. don't care t rhcp edo page mode early write cycle note : d out = open t rasp t rp t crp t rcd t cas v ih- v il- ras v ih- v il- cas t cas t cas t cp t cp t pc t pc t rsh t asr t rad t rah t asc t cah t csh t asc t asc t cah t cah t wcs t wp t wch t wcs t wcs t wch t wch t wp t wp t ds t ds t ds t dh t ds t ds v ih- v il- address v ih- v il- we v ih- v il- oe dq v ih- v il- row addr. column address column address column address valid data-in valid data-in valid data-in don't care t rhcp
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 14 - edo page mode read - modify - write cycle note : d out = open t rasp t rp v ih- v il- ras v ih- v il- cas don't care t csh t rcd t cas t cp t cas t rsh t crp t rad t rah t asr t asc t cah t asc t cah t ral t prwc t rcs t wp t cwl t wp t cwl t rwl t cwd t awd t rwd t oea t cwd t awd t cpwd t oea t oeh t rac t aa t cac t oez t oed t ds t dh t aa t cac t oez t oed t ds t dh t clz t clz valid data-out valid data-in valid data-out valid data-in row addr. col. addr. col. addr. v ih- v il- address v ih- v il- we v ih- v il- oe v i/oh- v i/ol- dq edo page read and write mixed ccycle t rasp t rp t cas t hpc t cas t cas t cp t cp t cp t asr t hpc t hpc t rah t asc t cah t asc t asc t asc t cah t cah t cah t rcs t rch t rcs t rch t rch t wcs t wch t wpe t cpa t clz t wed t wez t rac t aa t cac t oea t wez t ds t dh t aa t rez valid data-out valid data-out valid data-out valid data-in row addr col. addr column address column address column address v ih- v il- v ih- v il- v ih- v il- v ih- v il- v ih- v il- v i/oh- v i/ol- ras cas address we oe dq 0 ~ dq 3 don't care
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 15 - cas - before - ras refresh cycle v ih- v il- ras t ras t ras t rp t rp t rc t rc t csr t csr t chr t chr t rpc t rpc t crp v ih- v il- cas t wrh t wrp v ih- v il- we t wrp t wrh remark address , oe : don?t care dq : hi - z ras -only refresh cycle v ih- v il- ras t ras t ras t rp t rp t rc t rc t rpc t crp v ih- v il- cas t crp t asr t asr t rah t rah row address row address address v ih- v il- remark we, oe : don?t care dq : hi - z hidden refresh cycle ( read ) t rp t crp t rcd v ih- v il- ras v ih- v il- ucas,lcas t rac v ih- v il- address v ih- v il- we v ih- v il- oe dq v ih- v il- row address don't care t rp t cac t rcs t asc t cah t asr t cah t rad t ral t rsh t chr t rc t ras t ras column address t rc t wrh t aa t oea t clz t rez t cez t wez t oez data-out open t wrp t rrh
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 16 - hidden refresh cycle ( write ) note : d out = open t rp t crp t rcd v ih- v il- ras v ih- v il- ucas,lcas t ds v ih- v il- address v ih- v il- we v ih- v il- oe dq v ih- v il- row address don't care t rp t dh t wp t wch t wcs t asc t cah t asc t cah t rad t rsh t rsh t chr t rc t ras t ras column address data-in t wrp t wrh
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 17 - cas-before ras refresh counter test cycle t cas t cpt v ih- v il- ras v ih- v il- cas t rp t ras t csr t chr t rsh t ral t asc t aa t cac t rcs t rrh t rch t wrp t wrh t wrh t wrp t oea t cez t oez t clz t rwl t cwl t wch t wcs t wp t ds t dh t rcs t awd t cwd t rwl t cwl t wp t dh t ds t oed t oez t clz t cac t aa t oea open column address valid data-out valid data-in don't care valid data-in valid data-out v ih- v il- address v ih- v il- we v ih- v il- oe v oh- v ol- dq v ih- v il- we v ih- v il- oe v ih- v il- dq v ih- v il- we v ih- v il- oe v i/oh- v i/ol- dq read cycle write cycle read-modify-write t cah t wrp t wrh
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 18 - test mode in cycle t rp t rc t ras t rp t rpc t cp t csr t chr t wts t wth t cez open t rpc don't care v ih- v il- v ih- v il- v ih- v il- v i/oh- v i/ol- ras cas we dq test mode by using the test mode, the test time can be reduced. the reason for this is that, the memory emulates the x 16-bit organization during test mode. don?t care about the input levels of the cas input a0, a1 . (1) setting the mode executing the test mode cycle ( we , cas before ras refresh cycle ) sets the test mode. (2) write / read operation when either a ?0? or a ?1? is written to the input pin in test mode, this data is written to 16 bits of memory cell. next, when the data is read from the output pin at the same address, the cell be checked. output = ?1? normal write (all memory cells) output = ?0? abnormal write (3) refresh refresh in the test mode must be performed with the ras / cas cycle or with the we, cas before ras refresh cycle. the we, cas before ras refresh cycle use the same counter as the cas before ras refresh?s internal counter. (4) mode cancellation the test mode is cancelled by executing one cycle of ras only refresh cycle or cas before ras refresh cycle.
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 19 - cas-before-ras self refresh cycle t rps t rass t rp t rpc t cp t csr t cez open t rpc don't care v ih- v il- v ih- v il- v i/oh- v i/ol- ras cas dq t chs t wrp t wrh v ih- v il- we note : oe , address = don?t care
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 20 - ordering information part number speed power feature temperature package GLT4160M04-60J3 60ns normal edo commercial soj 300mil 26(24)l glt4160m04-70j3 70ns normal edo commercial soj 300mil 26(24)l glt4160m04e-60j3 60ns normal edo extended soj 300mil 26(24)l glt4160m04e-70j3 70ns normal edo extended soj 300mil 26(24)l glt4160m04-60tc 60ns normal edo commercial tsopii 300mil 26(24)l glt4160m04-70tc 70ns normal edo commercial tsopii 300mil 26(24)l glt4160m04e- 60tc 60ns normal edo extended tsopii 300mil 26(24)l glt4160m04e- 70tc 70ns normal edo extended tsopii 300mil 26(24)l parts numbers (top mark) definition : glt 4 160 m 04 e - 60 j3 note : c cdrom , h hdd. example : 1.glt710008- 15t 1mbit(128kx8)15ns 5v sram pdip(300mil)package type. 2.glt44016- 40j4 4mbit(256kx16)40ns 5v dram soj(400mil)package type. 4 : dram 6 : standard sram 7 : cache sram 8 : synchronous burst sram -sram 064 : 8k 256 : 256k 512 : 512k 100 : 1m -dram 10 : 1m(c/edo)* 11 : 1m(c/fpm)* 12 : 1m(h/edo)* 13 : 1m(h/fpm)* 20 : 2m(edo) 21 : 2m(fpm) 40 : 4m(edo) 41 : 4m(fpm) 80 : 8m(edo) 81 : 8m(fpm) 160 : 16m(edo) 161 : 16m(fpm) *see note voltage blank : 5v l : 3.3v m : 2.5v n : 2.1v config. 04 : x04 08 : x08 16 : x16 32 : x32 speed -sram 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -dram 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns package t : pdip(300mil) ts : tsop(type i) tc : tsop(type ll) pl : plcc fa : 300mil sop fb : 330mil sop fc : 445mil sop j3 : 300mil soj j4 : 400mil soj p : pdip(600mil) q : pqfp tq : tqfp temperature range e : extended temperature i : industrial temperature blank : commercial temperature
g-link glt4160m04 4m x 4 cmos dynamic ram with extended data output jan 2000 (rev. 1.3) g-link technology 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 21 - package information 300mil 24/26 lead thin small outline package soj 300mil 24/26 lead thin small outline package (tsop) type ii

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